WM8904 Datasheet, PDF (99/188 Pages) Wolfson Microelectronics plc – Ultra Low Power CODEC for Portable Audio Applications

Pre-Production
WM8904
REGISTER BIT
ADDRESS
R27 (1Bh)
11
Audio
Interface 3
LABEL
LRCLK_DIR
DEFAULT
0
10:0 LRCLK_RATE 000_0100
[10:0]
_0000
Table 56 Digital Audio Interface Clock Control
DESCRIPTION
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
LRC Rate (Master Mode)
LRC clock output = BCLK / LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
COMPANDING
The WM8904 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides
as shown in Table 57.
REGISTER BIT
ADDRESS
R24 (18h)
3
Audio
Interface 0
LABEL
ADC_COMP
2
ADC_COMPMODE
1
DAC_COMP
0
DAC_COMPMODE
Table 57 Companding Control
DEFAULT
DESCRIPTION
0
ADC Companding Enable
0 = disabled
1 = enabled
0
ADC Companding Type
0 = µ-law
1 = A-law
0
DAC Companding Enable
0 = disabled
1 = enabled
0
DAC Companding Type
0 = µ-law
1 = A-law
Companding involves using a piecewise linear approximation of the following equations (as set out by
ITU-T G.711 standard) for data compression:
-law (where =255 for the U.S. and Japan):
F(x) = ln( 1 + |x|) / ln( 1 + )
-1 ≤ x ≤ 1
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA)
1/A ≤ x ≤ 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of
data.
Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).
8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows
samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B,
8-bit data words may be transferred consecutively every 8 BCLK cycles.
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PP, Rev 3.3, September 2012
99