WM8904 Datasheet, PDF (93/188 Pages) Wolfson Microelectronics plc – Ultra Low Power CODEC for Portable Audio Applications

Pre-Production
WM8904
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 46 Left Justified Audio Interface (assuming n-bit word length)
In I²S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
LRCLK
BCLK
DACDAT/
ADCDAT
LEFT CHANNEL
1/fs
RIGHT CHANNEL
1 BCLK
1
2
MSB
3
n-2 n-1 n
Input Word Length (WL)
LSB
1 BCLK
1
2
3
n-2 n-1 n
Figure 47 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1^st (mode B) or 2^nd (mode A) rising edge
of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 48 and
Figure 49. In device slave mode, Figure 50 and Figure 51, it is possible to use any length of frame
pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK
period before the rising edge of the next frame pulse.
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PP, Rev 3.3, September 2012
93