WM9703 Datasheet, PDF (8/30 Pages) Wolfson Microelectronics plc – AC97 Revision 2.1 Audio Codec

WM9703
WARM RESET
SYNC
t_{SYNC_HIGH}
t_SYNC2CLK
Production Data
BIT_CLK
Figure 3 Warm Reset Timing
PARAMETER
SYNC active high pulse width
SYNC inactive to BIT_CLK start-
up delay
SYMBOL
tSYNC_HIGH
tSYNC2_CLK
MIN
162.4
TYP
1.3
CLOCK SPECIFICATIONS
BIT_CLK
SYNC
t_{CLK_HIGH}
t_{CLK_PERIOD}
t_{SYNC_HIGH}
t_{CLK_LOW}
t_{SYNC_LOW}
t_{SYNC_PERIOD}
MAX
UNIT
µs
ns
Figure 4 Clock Specifications (50pF External Load)
Note: Worst case duty cycle restricted to 40/60.
PARAMETER
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BIT_CLK high pulse width (Note 1)
BIT_CLK low pulse width (Note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
SYMBOL
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSYNC_HIGH
tSYNC_LOW
MIN
32.56
32.56
TYP
12.288
81.4
40.7
40.7
48.0
20.8
1.3
19.5
MAX
750
48.84
48.84
UNIT
MHz
ns
ps
ns
ns
kHz
µs
µs
µs
WOLFSON MICROELECTRONICS LTD
PD Rev 3.4 January 2001
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