WM9703 Datasheet, PDF (13/30 Pages) Wolfson Microelectronics plc – AC97 Revision 2.1 Audio Codec

Production Data
WM9703
Signals from the PCM DAC channels do not have stereo enhancement applied. It is assumed that
these signals will already have been processed digitally with any required 3D enhancement effect.
Applying the analogue 3D enhancement will corrupt this digital effect. This is equivalent to setting the
POP bit in register 20h. As a result, the readback value of this bit is fixed as 1, and attempts to
change it will be ignored. POP bit is set to one and cannot be re-set.
VARIABLE SAMPLE RATE SUPPORT
The DACs and ADCs on this device support all the recommended sample rates specified in the Intel
Revision 2.1 specification for both audio and modem rates. Default rates are 48ks/s. If alternative
rates are selected, the AC’97 interface continues to run at 48k words per second, but data is
transferred across the link in bursts such that the net sample rate selected is achieved. It is up to the
AC’97 Revision 2.1 compliant controller to ensure that data is supplied to the AC link, and received
from the AC link, at the appropriate rate.
The device supports on demand sampling. That is, when the DAC signal processing circuits need
another sample, a sample request is sent to the controller which must respond with a data sample in
the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will
request a sample from the controller every other frame, for each of the stereo DACs. Note that if an
unsupported rate is written to one of the rate registers, the rate will default to the nearest rate
supported. The register will then respond when interrogated with the supported rate the device has
defaulted to.
ADCs are controlled similarly but with one difference: Normally the left and right channel ADCs
sample at the same rate.
AUDIO
SAMPLE RATE
8000
11025
16000
22050
44100
48000
CONTROL VALUE
D15-D0
1F40
2B11
3E80
5622
AC44
BB80
Table 3 Variable Sample Rates Supported
MODEM
SAMPLE RATE
7200
8228.57 (57600/7)
8400
9000
9600
10285.71 (72000/7)
12000
13714.28 (96000/7)
19200
24000
CONTROL VALUE
D15-D0
1C20
2024
20D0
2328
2580
282D
2EE0
3592
4B00
5DC0
The following table shows which registers control which DAC rates, versus Mode and ID selected
CODEC ID
00 and 01
10
11
FRONT DAC RATE REGISTER
2Ch
2Eh
2Ch (centre) and 30h (LFE)
Table 4 Variable Rate Register Location Versus ID
ADC RATE REG
32h
WOLFSON MICROELECTRONICS LTD
PD Rev 3.4 January 2001
13