WM8170 Datasheet, PDF (8/41 Pages) Wolfson Microelectronics plc – 3.3V Integrated Signal Processor for Area Array CCDs

WM8170
OUTPUT DATA
Product Preview Rev 1.0
SHD
DCLK
OEB
D[9:0],
RETIME=0
D[9:0],
RETIME=1
PTDO,
RETIME=0
PTDO,
RETIME=1
t_SHDO
t_SHPT
Figure 2 Output Data Timing Diagram
t_SHDC
t_CKH
t_CKL
t_PER
t_DCDO
t_DCPT
t_PEZ
t_PZE
Test Characteristics
CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15kΩ , TA = 0^oC to +70^oC, unless otherwise stated.
PARAMETER
SYMBOL
DCLK period
DCLK high
DCLK low
Output propagation delay,
RETIME = 0, SHD trailing
edge to D[9:0] out
Output propagation delay,
RETIME = 1, DCLK leading
edge to D[9:0] out
Trailing edge of SHD to
leading edge of DCLK
Output disable time, OEB
rising to D[9:0] and PTDO
tristate
Output enable time, OEB
falling to D[9:0] and PTDO
out
PTDO propagation delay,
RETIME = 0, SHD trailing
edge to PTDO out
PTDO propagation delay,
RETIME=1, DCLK leading
edge to PTDO out
tPER
tCKH
tCKL
tSHDO
tDCDO
tSHDC
tPEZ
tPZE
tSHPT
tDCPT
TEST
CONDITIONS
MIN
47.6
19
19
TYP
23.0
11.2
8.3
6.8
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
8