WM8170 Datasheet, PDF (33/41 Pages) Wolfson Microelectronics plc – 3.3V Integrated Signal Processor for Area Array CCDs

WM8170
Product Preview Rev 1.0
CONTROL BIT TABLE
CONTROL BITS
DESCRIPTION
SOFTWARE RESET (000001)
A write to this register will force all registers to return to their default state.
SET UP REGISTER 1 (000010)
VCLP[1:0]
Controls the VCLP voltage output.
VCLP1
VCLP0
VCLP PIN
0
0
VRB
0
1
VMID
1
0
VRT
1
1
Reserved
ACINP
Enables the AC coupling resistor between DIN and VMID.
ACINP
0
No AC coupling resistor
1
AC coupling resistor
INVSHX
Enables the invert on SHD/SHP.
INVSHX
0
No invert, SHD / SHP active low
1
Invert, SHD / SHP active high
TIMES2
Enables additional 6dB gain in PGA.
TIMES2
0
No additional 6dB gain
1
Additional 6dB gain
POSVID
Allows the WM8170 to accept positive going video.
Default input video is negative.
POSVID
0
Input video negative going (Default)
1
Input video positive going
STOPDC
Enables or disables both the analogue and digital DC correction circuitry.
STOPDC
0
DC offset correction circuitry enabled
1
DC offset correction circuitry disabled
SET UP REGISTER 2 (000011)
RETIME
Enables the retiming of the digital outputs with DCLK.
RETIME
0
No retiming
1
Output data retimed
INVDIG
Digitally inverts the D[9:0] outputs.
INVDIG
0
No invert
1
Outputs inverted
PTDO[2:0]
Selects the signal output onto the PTDO Pin.
PTDO2
PTDO1
PTDO0 PTDO PIN
0
0
0
Threshold detect output
0
0
1
Out of range signal
0
1
0
Clip1 error - digital correction error (ADC output is outside the
digital correction range).
0
1
1
BLCENB error - caused by BLCENB going high before the
internal DC offset correction circuitry has finished.
1
0
0
Active low going, analogue DC loop enable pulse
1
0
1
Active low going, IIR enable pulse
1
1
0
Active low going, Area Define Pulse
1
1
1
Reserved for Test Purposes
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
33