WM9709 Datasheet, PDF (7/18 Pages) Wolfson Microelectronics plc – AC LINK INTERFACE AUDIO DAC

Production Data
RESETB
SDATAOUT
SDATAIN,
BITCLK
t_setup2rst
t_off
Hi-Z
WM9709
Figure 4 ATE Test Mode Timing
PARAMETER
Setup to trailing edge of RESETB
(also applies to SYNC)
Rising edge of RESETB to Hi-Z
delay
Notes:
SYMBOL
Tsetup2rst
Toff
MIN
15.0
-
TYP
-
-
MAX
-
25.0
UNIT
nS
nS
1. All WM9709 signals are normally low through the trailing edge of RESETB. Bringing
SDATAOUT high for the trailing edge of RESETB causes WM9709’s AC-link outputs to go high
impedance, which is suitable for ATE in circuit testing.
2. A vendor specific internal test mode can be entered by bringing SYNC high for the trailing edge
of RESETB. This mode has no effect on WM9709 AC-link output signal levels.
3. Once either of the two test modes have been entered, WM9709 must be issued another
RESETB with all AC-link signals low to return to the normal operating mode.
SIGNAL RISE AND FALL TIMES
trise_CLK
BITCLK
trise_SYNC
SYNC
trise_DIN
SDATAIN
trise_DOUT
SDATAOUT
tfall_CLK
tfall_SYNC
tfall_DIN
tfall_DOUT
Figure 5 Signal Rise and Fall Times (50pF external load)
w
PD Rev 1.3 February 2003
7