WM9709 Datasheet, PDF (11/18 Pages) Wolfson Microelectronics plc – AC LINK INTERFACE AUDIO DAC

Production Data
WM9709
When mono audio sample streams are output from the AC-link controller, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
SLOT 1: COMMAND ADDRESS PORT
Bit(19)
Bit(18:12)
Bit(11:0)
Read/write command (1 = read, 0 = write)
Control register index (64 16-bit locations, addressed
on even byte boundaries)
Reserved (stuffed with 0s)
The first bit (MSB) sampled by WM9709 indicates whether the current control transaction is a read
or write operation. The following 7 bit positions communicate the targeted control register address.
The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC-link
controller.
In the case of the WM9709, read mode is required only to access the vendor ID register
SLOT 2: COMMAND DATA PORT
The Slot 2 command data port is not normally used by WM9709.
SLOTS 3 & 4: PCM PLAYBACK LEFT & RIGHT CHANNELS
Audio output frame slots 3 & 4 are the composite digital audio left and right playback streams. In a
typical ‘Games Compatible’ PC this slot is composed of standard PCM (.wav) output samples
digitally mixed (on the AC-link controller or host processor) with music synthesis output samples. If a
sample stream of resolution less than 20-bits is transferred, the AC-link controller must stuff all
trailing non-valid bit positions within this time slot with 0s. When WM9709 pin 2 (ID) is held low, data
from slots 3 & 4 is mapped onto the DAC inputs.
SLOTS 5: OPTIONAL MODEM LINE CODEC
Audio output frame slot 5 would typically contain the MSB justified modem DAC input data. This
optional AC’97 feature is not supported in WM9709, and data is ignored if written to this location.
SLOTS 6 & 9: PCM PLAYBACK CENTRE AND LFE CHANNELS
Audio data corresponding to surround centre and LFE channels is contained in slots 6 & 9. When pin
2 (ID) is left high impedance (not driven), data from these slots is mapped onto the DAC inputs. In
this mode BITCLK is an input from the AC-link MASTER.
SLOTS 7 & 8: PCM PLAYBACK SURROUND LEFT & RIGHT CHANNELS
Audio data corresponding to surround left and right channels is contained in slots 7 & 8. When pin 2
(ID) is pulled high, data from these slots is mapped onto the DAC inputs. In this mode BITCLK is an
input from the AC-link MASTER.
AC-LINK AUDIO INPUT FRAME (SDATAIN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC-link controller. As is the case for an audio output frame, each AC-link audio input
frame consists of 12, 20-bit time slots. The WM9709 supports a reduced set of these audio input
frames, specifically slots 0,1 and 2.
The first bit within slot 0 is a global bit (SDATAIN slot 0, bit 15) which flags whether WM9709 is in
the “DAC Ready” state or not. If the “DAC Ready” bit is a 0, this indicates that WM9709 is not ready
for normal operation. When the AC-link “DAC Ready” indicator bit is a 1, it indicates that the AC-link
and WM9709 control and status registers are in a fully operational state.
Once WM9709 is sampled “DAC Ready” then the next 12 bit positions sampled by the AC-link
controller indicate which of the corresponding 12 time slots are assigned to input data streams, and
that they contain valid data. Figure 8 illustrates the time slot based AC-link protocol.
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PD Rev 1.3 February 2003
11