WM9714L_06 Datasheet, PDF (67/94 Pages) Wolfson Microelectronics plc – AC 97 Audio CODEC

Pre-Production
WM9714L
LOW POWER STANDBY MODE
If all the bits in registers 26h, 3Ch and 3Eh are set except VMID1M (register 3Ch, bit 14), then the
WM9714L is in low-power standby mode and consumes very little current. A 1MΩ resistor string
remains connected across AVDD to generate VREF. This is necessary if the on-chip analogue
comparators are used (see “Battery Alarm and Battery Measurement” section), and helps shorten the
delay between wake-up and playback readiness. If VREF is not required, the 1MΩ resistor string can
be disabled by setting the VMID1M bit, reducing current consumption further.
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM9714L can run from 1.8V to 3.6V. By default, all analogue circuitry
on the IC is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to
1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents
used in the analogue circuitry. This is controlled as shown below.
REGISTER
ADDRESS
5Ch
BIT
6:5
LABEL DEFAULT
VBIAS 00
Table 62 Analogue Bias Selection
DESCRIPTION
Analogue Bias optimization
11 : Lowest bias current, optimized for 1.8V
10 : Low bias current, optimized for 2.5V
01, 00 : Default bias current, optimized for 3.3V
POWER ON RESET (POR)
The WM9714L has an internal power on reset (PORB) which ensures that a reset is applied to all
registers until a supply threshold has been exceeded. The POR circuitry monitors the voltage for both
AVDD and DCVDD and will release the internal reset signal once these supplies are both nominally
greater than 1.36V. The internal reset signal is an AND of the PORB and RESETB input signal.
It is recommended that for operation of the WM9714L, all device power rails should be stable before
configuring the device for operation.
AC97 INTERFACE TIMING
Test Characteristics:
DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25°C to +85°C, unless otherwise
stated.
CLOCK SPECIFICATIONS
BITCLK
SYNC
t_{CLK_HIGH}
t_{CLK_PERIOD}
t_{SYNC_HIGH}
t_{CLK_LOW}
t_{SYNC_LOW}
t_{SYNC_PERIOD}
Figure 20 Clock Specifications (50pF External Load)
w
PP Rev 3.0 June 2006
67