WM9714L_06 Datasheet, PDF (17/94 Pages) Wolfson Microelectronics plc – AC 97 Audio CODEC

Pre-Production
WM9714L
REGISTER
ADDRESS
46h
BIT
15:12
LABEL
N[3:0]
11
LF
10
SDM
9
DIVSEL
8
DIVCTL
6:4
PGADDR
3:0
PGDATA
Table 4 PLL Clock Control
INTEGER N MODE
DEFAULT
DESCRIPTION
0000
0 = off
0 = off
0 = off
0
000
0000
PLL integer division control (must be set
between 05h and 0Ch for integer N mode)
Allows PLL operation with low frequency
input clocks (< 8.192MHz)
Sigma Delta Modulator enable. Allows
fractional N division
Enables input clock to PLL to be divided by
2 or 4. Use if input clock is above 14.4MHz
Controls division mode when DIVSEL is
high. 0 = div by 2, 1= div by 4.
Pager address bits to access programming
of K[21:0] and SPLL[6:0]
Pager data bits
The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz which is divided by 4 to achieve
a nominal system clock of 24.576MHz.
The integer division ratio (N) is determined by: FPLL_out / FPLL_IN , and is set by N[3:0] and must be in
the range 5 to 12 for integer N operation (0101 = div by 5, 1100 = div by 12). Note that setting LF=1
enables a further division by 4 required for input frequencies in the range 2.048MHz – 4.096MHz.
Integer N mode is selected by setting SDM=0.
FRACTIONAL N MODE
Fractional N mode provides a divide resolution of 1/2²² and is set by K[21:0] (register 46h, see
section). The relationship between the required division X, the fractional division K[21:0] and the
integer division N[3:0] is:
K = 2²² (X − N )
where 0 < (X – N) < 1 and K is rounded to the nearest whole number.
For example, if the PLL_IN clock is 13MHz and the desired PLL_OUT clock is 98.304MHz then the
desired division, X, is 7.5618. So N[3:0] will be 7h and K[21:0] will be 23F488h to produce the desired
98.304MHz clock (see Table 5).
INPUT CLOCK (PLL_IN)
DESIRED
PLL
OUTPUT
(PLL_OUT)
DIVISION
REQUIRED
(X)
FRACTIONAL
DIVISION (K)
INTEGER
DIVISION (N)
2.048MHz
98.304MHz
48
0
12x4*
4.096MHz
98.304MHz
24
0
6x4*
12.288MHz
98.304MHz
8
0
8
13MHz
98.304MHz
7.5618
0.5618
7
27MHz (13.5MHz)**
98.304MHz
7.2818
0.2818
7
*Divide by 4 enabled in PLL feedback path for low frequency inputs. (LF = 1)
**Divide by 2 enabled at PLL input for frequencies > 14.4MHz > 38MHz (DIVSEL = 1, DIVCTL = 0)
Table 5 PLL Modes of Operation
w
PP Rev 3.0 June 2006
17