WM8974_07 Datasheet, PDF (66/87 Pages) Wolfson Microelectronics plc – Mono CODEC with Speaker Driver

WM8974
Production Data
ADDR
REGISTER
B8
B[15:9]
NAME
B7
B6
B5
B4
B3
B2
B1
B0 DEF’T
VAL
DEC HEX
(HEX)
54 36 SPK volume ctrl
0
SPKZC SPKMUTE
SPKVOL
039
56 38 MONO mixer ctrl
0
0
MONO
0
0
0
AUX2
BYP2
DAC2 000
MUTE
MONO MONO MONO
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER BIT
ADDRESS
0 (00h)
[8:0]
1 (01h)
8
LABEL
RESET
BUFDCOPEN
7
6
AUXEN
5
PLLEN
4
MICBEN
3
BIASEN
2
BUFIOEN
1:0 VMIDSEL
2 (02h)
8:5
4
BOOSTEN
3
2
INPPGAEN
1
0
ADCEN
3 (03h)
8
DEFAULT
DESCRIPTION
N/A
0
0
0
0
0
0
0
00
0000
0
0
0
0
0
0
Software reset
Dedicated buffer for DC level shifting output stages when in
1.5x gain boost configuration.
0=Buffer disabled
1=Buffer enabled (required for 1.5x gain boost)
Reserved
Auxilliary input buffer enable
0 = OFF
1 = ON
PLL enable
0=PLL off
1=PLL on
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Analogue amplifier bias control
0=Disabled
1=Enabled
Unused input/output tie off buffer enable
0=Disabled
1=Enabled
Reference string impedance to VMID pin:
00=off (open circuit)
01=75kΩ
10=300kΩ
11=2.5kΩ
Reserved
Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Reserved
Input microphone PGA enable
0 = disabled
1 = enabled
Reserved
ADC Enable Control
0 = ADC disabled
1 = ADC enabled
Reserved
REFER TO
Resetting the Chip
Analogue Outputs
Auxiliary Inputs
Master Clock and
Phase Locked Loop
(PLL)
Microphone Biasing
Circuit
Power
Management
Enabling the
Outputs
Power
Management
Input Boost
Input Signal Path
Analogue to Digital
Converter (ADC)
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PD Rev 4.2 March 2007
66