WM8974_07 Datasheet, PDF (52/87 Pages) Wolfson Microelectronics plc – Mono CODEC with Speaker Driver

WM8974
Production Data
REGISTER BIT
ADDRESS
R6
0
Clock generation
control
LABEL
MS
4:2 BCLKDIV
7:5 MCLKDIV
8
CLKSEL
Table 48 Clock Control
DEFAULT
DESCRIPTION
0
Sets the chip to be master over FRAME and
BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs
generated by the WM8974 (MASTER)
000
Configures the BCLK and FRAME output
frequency, for use when the chip is master
over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
010
Sets the scaling for either the MCLK or PLL
clock output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
1
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Note that the setting MCLKDIV=000 and BCLKDIV=000 must not be used simultaneously.
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8974 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
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PD Rev 4.2 March 2007
52