WM8593_07 Datasheet, PDF (64/98 Pages) Wolfson Microelectronics plc – 24-bit 192kHz 2Vrms Multi-Channel CODEC

WM8593
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R8 (08h) – DAC2 Control Register 2 (DAC2_CTRL2)
Bit #
15
14
13
12
11
10
9
8
Read
0
0
0
0
0
0
0
0
Write
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Default
0
0
0
0
0
0
0
0
Bit #
7
Read
0
Write
N/A
Default
0
Function
DAC2_SR[2:0]
DAC2_BCLKDIV[2:0]
6
5
4
3
2
1
0
0
DAC2_BCLKDIV[2:0]
N/A
DAC2_SR[2:0]
0
0
0
0
0
0
0
N/A = Not Applicable (no function implemented)
Description
DAC2 MCLK:LRCLK Ratio
000 = Auto detect
001 = 128fs
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = 1152fs
DAC2 BCLK Rate
000 = MCLK / 4
001 = MCLK / 8
010 = 32fs
011 = 64fs
100 = 128fs
All other values of DAC2_BCLKDIV[2:0] are reserved
Figure 32 R8 – DAC2 Control Register 2
R9 (09h) – DAC2 Control Register 3 (DAC2_CTRL3)
Bit #
15
14
13
12
11
10
9
8
Read
0
0
0
0
0
0
0
0
Write
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Default
0
0
0
0
0
0
0
0
Bit #
7
Read
0
Write
N/A
Default
0
Function
DAC2_MSTR
6
5
4
3
2
1
0
0
0
0
0
0
0
DAC2_MSTR
N/A
N/A
N/A
N/A
N/A
N/A
0
0
0
0
0
0
0
N/A = Not Applicable (no function implemented)
Description
DAC2 Master Mode Select
0 = Slave mode, DACBCLK2 and DACLRCLK2 are inputs to WM8593
1 = Master mode, DACBCLK2 and DACLRCLK2 are outputs from WM8593
Figure 33 R9 – DAC2 Control Register 3
w
PP Rev 1.0 January 2007
64