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WM8215 Datasheet, PDF (6/31 Pages) Wolfson Microelectronics plc – 60MSPS 10-bit 3-Channel CCD Digitiser
WM8215
ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
CONDITIONS
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate
Full-scale input voltage range
LOWREFS=0, Max Gain
(see Note 1)
LOWREFS=0, Min Gain
LOWREFS=1, Max Gain
LOWREFS=1, Min Gain
Input signal limits (see Note 2)
VIN
Input capacitance
AGND-0.3
Input switching impedance
Full-scale transition error
Gain = 0dB;
PGA[8:0] = 14(hex)
Zero-scale transition error
Gain = 0dB;
PGA[8:0] = 14(hex)
Differential non-linearity
DNL
Integral non-linearity
INL
Channel to channel gain matching
Output noise
Min Gain
Max Gain
References
Upper reference voltage
VRT
LOWREFS=0
1.95
LOWREFS=1
Lower reference voltage
VRB
LOWREFS=0
0.95
LOWREFS=1
Input return bias voltage
VRX
Diff. reference voltage (VRT-VRB)
VRTB
LOWREFS=0
0.95
LOWREFS=1
0.57
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
RLCDAC resolution
RLCDAC step size, RLCDACRNG
=0
VRLCSTEP
TYP
MAX
UNIT
60
MSPS
0.25
Vp-p
3.03
Vp-p
0.15
Vp-p
1.82
Vp-p
AVDD+0.3
V
10
pF
45

20
mV
20
mV
0.75
LSB
2
LSB
1%
%
0.2
LSB rms
2.15
LSB rms
2.05
2.25
V
1.85
V
1.05
1.25
V
1.25
V
1.25
V
1.0
1.10
V
0.6
0.68
V
1

45
2
3
4
0.173

mA

1
A
bits
V/step
RLCDAC step size, RLCDACRNG
=1
VRLCSTEP
LOWREFS = 0
LOWREFS = 1
0.11
0.10
V/step
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCBOT
0.4
V
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
LOWREFS = 0
LOWREFS = 1
V
0.4
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
3.0
V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
LOWREFS = 0
LOWREFS = 1
2.05
V
1.85
RLCDAC
DNL
-0.5
+0.5
LSB
RLCDAC
INL
+/-0.5
LSB
Notes:
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
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PD, Rev 4.3, September 2012
6