WM8960 Datasheet, PDF (48/92 Pages) Wolfson Microelectronics plc – Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications

WM8960
For further details of the Jack detect operation see the Headphone Switch section.
Production Data
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8960 and outputting ADC data
from it. It uses five pins:
 ADCDAT: ADC data output
 ADCLRC: ADC data alignment clock
 DACDAT: DAC data input
 DACLRC: DAC data alignment clock
 BCLK: Bit clock, for synchronisation
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8960 operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
ADCLRC can also be configured as a GPIO pin. In this case, the ADC will use DACLRC as a frame
clock. The ADCLRC/GPIO1 pin function should not be modified while the ADC is enabled.
Four different audio data formats are supported:
 Left justified
 Right justified

I²S
 DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8960 can be configured as either a master or slave mode device. As a master device the
WM8960 generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data transfer
on ADCDAT and DACDAT. In slave mode, the WM8960 responds with data to clocks it receives over
the digital audio interface. The mode can be selected by writing to the MS bit. Master and slave
modes are illustrated below.
WM8960
CODEC
BCLK
ADCLRC
DACLRC
ADCDAT
DACDAT
DSP
ENCODER/
DECODER
Note: The ADC and DAC can run at different sample rates
Figure 22 Master Mode
WM8960
CODEC
BCLK
ADCLRC
DACLRC
ADCDAT
DACDAT
DSP
ENCODER/
DECODER
Note: The ADC and DAC can run at different sample rates
Figure 23 Slave Mode
OPERATION WITH ADCLRC AS GPIO
When ALRCGPIO=1, the DACLRC pin is used as a frame clock for ADCs and DACs as shown below.
The ADCs and DACs must operate at the same sample rate in this mode. See Table 32 for details of
GPIO pin configuration.
Figure 24 Master Mode with ADCLRC as GPIO Figure 25 Slave Mode with ADCLRC as GPIO
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PD, August 2013, Rev 4.2
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