WM8803 Datasheet, PDF (37/45 Pages) Wolfson Microelectronics plc – DIGITAL AUDIO INTERFACE RECEIVER

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WM8803
If E/INT is set up for high level output when an interrupts are generated with INTOPF, the high-level
state will be maintained until the interrupt event output (address 0xEB) is read out. When that data
has been read, the E/INT output will return to the normal low level.
The channel status update flag is computed by comparing the current data with the first 48bits of the
previous block, and determining the channel status to have been updated if the data is the same.
READ REGISTER TABLE
The table below lists the read registers.
OUTPUT REGISTER
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
DO10
DO11
DO12
DO13
DO14
DO15
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
DO24
…..
DO54
DO55
DO56
…..
DO86
DO87
0XEB
0
OUTERR
OUTPCM
OUTEMP
OUTVFL
OUTFSC
OUTCSF
OUTSQY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0XEC
0
OUTERR
OUTPCM
0
FSCAL0
FSCAL1
FSCAL2
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
…..
Bit 46
Bit 47
0
0
0
0
0XED
CRC
CRC
0
0
0
0
0
0
Control
Control
Control
Control
Address
Address
Address
Address
Track
Track
Track
Track
Track
Track
Track
Track
Index
…..
Frame
Frame
zero
…..
abs frame
abs frame
Table 20 List of Read Registers
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PP Rev 1.1 September 2003
37