WM8803 Datasheet, PDF (11/45 Pages) Wolfson Microelectronics plc – DIGITAL AUDIO INTERFACE RECEIVER

Product Preview
CLOCKS
WM8803
PLL (LPF)
The WM8803 includes a VCO (voltage controlled oscillator) that can synchronize with data
corresponding to sampling frequencies from 30k to 195kHz.
The locking frequency is selected by setting PLLCK[1:0].
The VCO circuit can be stopped by setting PLLOPR.
The range of input data that can be received depends upon the settings of the PLLCK[1:0].
The (512/2)fs entry for the PLLCK[1:0] = “11” in Table 3 is a state where the PLL itself is
synchronized with the 512fs clock, but the clock signal output from CLKOUT is a frequency 1/2 that
of the PLL locked frequency i.e.256fs. This (512/2)fs lock frequency has the same functions as the
256fs setting from CLKOUT and can be convenient for certain applications. Refer to the output
clocks section for details.
It is recommended that the 256fs setting of PLLCK[1:0] = “00” is used to reduce the system power
consumption, especially in portable equipment.
For best performance, it is recommended that the 512fs setting of PLLCK[1:0] = “10” or the (512/2)fs
of PLLCK[1:0] = “11” is used.
PLLCK1 PLLCK0
PLL LOCK FREQUENCY
INPUT DATA RECEPTION RANGE
0
0
256fs
30k to 195kHz
0
1
384fs
30k to 108kHz
1
0
512fs
30k to 108kHz
1
1
(512/2)fs
30k to 108kHz
Table 3 Input Data Reception Ranges by PLL Lock Frequency Setting
The LPF is the PLL loop filter connection. Use capacitor and resistor components of the
recommended values as listed in the table below according to the PLLCK[1:0] settings used.
PLLCK1
0
0
1
PLLCK0
0
1
0
1
1
Table 4 Loop Filter Component Values
R0
150Ω
150Ω
C0
0.047µF
0.068µF
C1
0.0068µF
0.0047µF
LPF
R₀
C₁
C₀
Figure 4 Loop Filter Structure
w
PP Rev 1.1 September 2003
11