WM8321 Datasheet, PDF (32/253 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8321
Production Data
The possible ‘ON’ events that may trigger the ON sequence are listed in Table 3. The ON sequence
is only permitted when the supply voltage PVDD exceeds a programmable threshold SYSOK. See
Section 24 for details of PVDD voltage monitoring.
The OFF sequence is the reverse of the ON sequence. Each DC-DC Converter, LDO Regulator or
GPIO output that is associated with a timeslot in the ON sequence is switched off in the reverse
sequence following an ‘OFF’ event. If CLKOUT is assigned to a timeslot in the ON sequence, then
this is disabled in the reverse (OFF) sequence also.
The possible ‘OFF’ events are listed in Table 3. Note that it is possible to modify the OFF sequence
by writing to the associated registers in the ON power state if required; this allows the OFF sequence
to be independent of the ON sequence.
The SLEEP sequence is the transition from ON to SLEEP power states. Each LDO and each DC-DC
Converter may be associated with any one of the available timeslots in the SLEEP sequence. This
determines the time, within the sequence, at which that DC Converter or LDO will be disabled
following a ‘SLEEP’ event.
The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can
also be associated with any one of the available timeslots in the SLEEP sequence. The possible
‘SLEEP’ events are listed in Table 3.
The WAKE sequence is the reverse of the SLEEP sequence. Each DC-DC Converter, LDO Regulator
or GPIO output that is associated with a timeslot in the SLEEP sequence is switched on in the
reverse sequence following a ‘WAKE’ event. If CLKOUT is assigned to a timeslot in the SLEEP
sequence, then this is disabled in the reverse (WAKE) sequence also.
The possible ‘WAKE’ events are listed in Table 3. Note that it is possible to modify the WAKE
sequence by writing to the associated registers in the SLEEP power state if required; this allows the
WAKE sequence to be independent of the SLEEP sequence.
Any DC-DC Converter or LDO that is not associated with one of the 5 timeslots in the ON sequence
may, instead, be configured to be hardware controlled via a GPIO pin configured as one of the
Hardware Enable inputs. See Section 21 for details of the GPIO functions. Any DC-DC Converter or
LDO that is not under Hardware control may be enabled or disabled under Software control in the ON
state, regardless of whether it is associated with any timeslot in the ON sequence.
When a valid OFF event occurs, any DC-DC Converter or LDO which is not allocated a timeslot in the
ON sequence is disabled immediately. This includes any DC-DC Converter or LDO which is under
GPIO (Hardware Enable) control. The only exception is LDO11 which may, optionally, be configured
to be enabled in the OFF state.
The WM8321 monitors the DC-DC Converters and LDOs during the ON sequence to ensure that the
required circuits have powered up successfully before proceeding to the next timeslot. The nominal
timeslot durations are extended if necessary in order to wait for the selected DC-DC Converters or
LDOs to power up. If the ON sequence has not completed within 2 seconds of starting the transition,
then a Power Sequence Failure has occurred, resulting in the OFF state being forced.
The most recent ON or WAKE event can be determined by reading the bits in the “ON Source”
register, R400Eh. The most recent OFF event can be determined by reading the bits in the “OFF
Source” register, R400Fh.
The “ON Source” register is updated when a new ON event occurs. The “OFF Source” register is
updated when a new OFF event occurs. Note that some Reset conditions (see Section 24) result in
an OFF transition followed by an ON transition; these events are recorded as Reset events in the “ON
Source” register.
w
PD, February 2012, Rev 4.0
32