WM8321 Datasheet, PDF (127/253 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

Production Data
WM8321
23.2.11 UNDERVOLTAGE INTERRUPTS
The primary UV_INT interrupt comprises fourteen secondary interrupts as described in
Section 15.12). The secondary interrupt bits are defined in Table 75.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a UV_INT interrupt. The secondary interrupt bits in R16403
(4013h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary
interrupts are all masked by default.
ADDRESS
R16403
(4013h)
Interrupt Status
3
R16404
(4014h)
Interrupt Status
4
R16411
(401Bh)
Interrupt Status
3 Mask
R16412
(401Ch)
Interrupt Status
4 Mask
BIT
LABEL
9:0 UV_LDOn_EINT
3:0 UV_DCm_EINT
9:0 IM_UV_LDOn_EINT
3:0 IM_UV_DCm_EINT
DESCRIPTION
LDOn Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
DC-DCm Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Notes:
1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1-LDO10).
2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC1-DC4).
Table 75 Undervoltage Interrupts
w
PD, February 2012, Rev 4.0
127