WM8590_06 Datasheet, PDF (31/51 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz Stereo CODEC

Production Data
WM8590
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to
write the same attenuation value to both left and right volume control registers, saving on software
writes.
REGISTER
ADDRESS
R14 (0Eh)
0001110
Attenuation
ADCL
BIT LABEL
7:0 LAG[7:0]
8
ZCLA
R15 (0Fh)
0001111
Attenuation
ADCR
7:0 RAG[7:0]
8
ZCRA
R21 (15h)
0
0010101
ADC Input Mux
1
MUTERA
MUTELA
2
ZCSCRR
3
ZCSCRL
8
LRBOTH
DEFAULT
11001111
(0dB)
0
11001111
(0dB)
0
0
0
0
0
0
DESCRIPTION
Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See
Table 10.
Left Channel ADC Zero Cross Enable:
0: Zero cross disabled
1: Zero cross enabled
Attenuation data for right channel ADC gain in 0.5dB steps. See
Table 10.
Right Channel ADC Zero Cross Enable:
0: Zero cross disabled
1: Zero cross enabled
Mute for Right Channel ADC
0: Mute Off
1: Mute on
Mute for Left Channel ADC
0: Mute Off
1: Mute on
Zero Cross reference for right channel
0: Zero Cross detector compares positive and negative
inputs
1: Zero Cross detector compares negative input to VMID
Zero Cross reference for left channel
0: Zero Cross detector compares positive and negative
inputs
1: Zero Cross detector compares negative input to VMID
Right Channel Input PGA Controlled by Left Channel Register
0: Right channel uses RAG and MUTERA
1: Right channel uses LAG and MUTELA
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PD Rev 4.0 January 2006
31