WM8590_06 Datasheet, PDF (20/51 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz Stereo CODEC

WM8590
Production Data
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN/
DOUT
LEFT CHANNEL
123
MSB
n-2 n-1 n
LSB
1/fs
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
Figure 12 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN is sampled by the WM8590 on the rising edge of DACBCLK
preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples
(Figure 13).
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
1/fs
LEFT CHANNEL
DIN/
DOUT
123
MSB
n-2 n-1 n
LSB
Figure 13 Right Justified Mode Timing Diagram
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
w
PD Rev 4.0 January 2006
20