WM8950 Datasheet, PDF (25/52 Pages) Wolfson Microelectronics plc – ADC WITH MICROPHONE INPUT AND PROGRAMMABLE DIGITAL FILTERS

Preliminary Technical Data
WM8950
ALC CLIP PROTECTION
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
clip protection function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain
is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls
below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
Note:
If ATK = 0000, then the clip protection circuit makes no difference to the operation of the ALC. It is
designed to prevent clipping when long attack times are used.
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8950 has a noise gate function that
prevents noise pumping by comparing the signal level at the input pins against a noise gate
threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to:
Signal level at input pin [dB] < NGTH [dB]
The PGA gain is then held constant (preventing it from ramping up as it normally would when the
signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. Note that the noise gate only works in conjunction with the ALC function.
REGISTER
ADDRESS
R35
ALC Noise Gate
Control
BIT
LABEL
2:0 NGTH
3 NGATEN
Table 15 ALC Noise Gate Control
DEFAULT
DESCRIPTION
000
Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
0
Noise gate function enable
1 = enable
0 = disable
GRAPHIC EQUALISER
A 5-band graphic EQ is provided, which can be applied to the ADC data under control of the
EQMODE register bit.
REGISTER BIT
ADDRESS
R18
8
EQ Control 1
Table 16 EQ Select
LABEL
EQMODE
DEFAULT
DESCRIPTION
1
0 = Equaliser applied to ADC data
1 = Equaliser bypassed
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PTD Rev 2.1 June 2005
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