WM8772_05 Datasheet, PDF (25/73 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz 6-Channel Codec with Volume Control

Production Data
WM8772EDS – 28 LEAD SSOP
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EDS on the rising edge of
BCLK preceding a LRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of BCLK preceding a LRC transition and may be sampled on the rising edge of BCLK.
LRC are high during the left samples and low during the right samples (Figure 24).
1/fs
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
LEFT CHANNEL
DIN1/2/3/
DOUT
123
MSB
n-2 n-1 n
LSB
Figure 24 Right Justified Mode Timing Diagram
RIGHT CHANNEL
123
MSB
n-2 n-1 n
LSB
I²S MODE
In I²S mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the second rising edge of
BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of BCLK following an LRC transition and may be sampled on the rising edge of
BCLK. LRC are low during the left samples and high during the right samples.
1/fs
DACLRC/
ADCLRC
LEFT CHANNEL
DACBCLK/
ADCBCLK
DIN1/2/3/
DOUT
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 25 I²S Mode Timing Diagram
RIGHT CHANNEL
1 BCLK
123
MSB
n-2 n-1 n
LSB
w
PD Rev 4.2 October 2005
25