WM8766 Datasheet, PDF (18/32 Pages) Wolfson Microelectronics plc – 24 BIT 192KHZ 6 CHANNEL DAC

WM8766
ZERO DETECT
Preliminary Technical Data
The WM8766 has a zero detect circuit for each DAC channel that detects when 1024 consecutive
zero samples have been input. The MUTE pin output may be programmed to output the zero detect
signal (see Table 9) which may then be used to control external muting circuits. A ‘1’ on MUTE
indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by
setting IZD.
DZFM[1:0]
MUTE
00
All channels zero
01
Channel 1 zero
10
Channel 2 zero
11
Channel 3 zero
Table 9 Zero Flag Output Select
SOFTWARE CONTROL INTERFACE OPERATION
The WM8766 is controlled using a 3-wire serial interface in software mode or pin programmable in
hardware mode.
The control mode is selected by the state of the MODE pin.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is
used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire
interface protocol is shown in Figure 16.
ML/I2S
MC/IWL
MD/DM
B15 B14 B13 B12 B11 B10 B9 B8 B7
B6 B5 B4 B3 B2
B1 B0
Figure 16 3-wire SPI Compatible Interface
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. ML/I2S is edge sensitive – the data is latched on the rising edge of ML/I2S.
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS BIT
0000010
3
DAC Channel Control
LABEL
ATC
DEFAULT
0
DESCRIPTION
Attenuator Control Mode:
0: Right channels use right
attenuations
1: Right channels use left
attenuations
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PTD Rev 2.3 February 2004
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