WM8987 Datasheet, PDF (14/59 Pages) Wolfson Microelectronics plc – Stereo CODEC for Portable Audio Applications

WM8987L
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
t_CSL
SCLK
t_SCY
t_SCH
t_SCL
Production Data
t_CSH
t_SCS
t_CSS
SDIN
t_DSU
t_DHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25^oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL
40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
ns
Pulse width of spikes that will be suppressed
tps
0
5
ns
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PD Rev 4.0 August 2008
14