WM8150_05 Datasheet, PDF (13/26 Pages) Wolfson Microelectronics plc – Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output

Production Data
WM8150
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.5V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 9 represents the processing of the video signal through the WM8150.
OUTPUT
INPUT
INVERT
SAMPLING OFFSET DAC PGA
BLOCK
BLOCK BLOCK
ADC BLOCK
BLOCK
D
V
V
V
x (4095/V )
D
2
1
2_X
3
+0 if PGA^FF^SS[1:0]=11 1
V
+_-
++
IN
analog
+4095 if PGAFS[1:0]=10
+2047 if PGAFS[1:0]=0x digital
OP[3:0]
CDS = 1
D2 = D1 if INVOP = 0
V
RESET
CDS = 0
PGA gain
A = 0.78+(PGA[7:0]*7.57)/255
D2 =4095-D1 if INVOP = 1
V
VRLC
VRLCEXT=1
VRLCEXT=0
Offset _{260mV*(DAC[7:0]-127.5)/127.5}
DAC
RLC
DAC
V
*RLCV[3:0] + V
RLCSTEP
RLCBOT
V is VINP voltage sampled on video sample
V^IN is VINP sampled during reset clamp
V^RESETis voltage applied to VRLC pin
VRLC
CDS, VRLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
Figure 9 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8150. The values of V1, V2 and V3 are often calculated in reverse order during device
setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then
adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is
set to position the reset level correctly during operation.
Note: Refer to WAN0123 for detailed information on device calibration procedures.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video.
V1
=
VIN - VRESET ................................................................... Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1
=
VIN - VVRLC .................................................................... Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
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PD Rev 4.1 February 2005
13