WM8325 Datasheet, PDF (120/254 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8325
Production Data
23 INTERRUPT CONTROLLER
The WM8325 has a comprehensive Interrupt logic capability. The dedicated I¯R¯Q¯ pin can be used to
alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be
individually enabled or masked. Following an interrupt event, the host processor should read the
interrupt registers in order to determine what caused the interrupt, and take appropriate action if
required.
The WM8325 interrupt controller has two levels:
Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by
setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger
condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register
bit. Note that reading the register does not clear the secondary interrupt.
Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts
associated with one particular circuit block). Each of the secondary interrupts can be individually
masked or enabled as an input to the corresponding primary interrupt. The primary interrupt register
R16400 (4010h) is read-only.
The status of the I¯R¯Q¯ pin reflects the logical NOR of the primary interrupts. A logic 0 indicates that
one or more of the primary interrupts is asserted. Each of the primary interrupts can be individually
masked or enabled as an input to the I¯R¯Q¯ pin output.
The I¯R¯Q¯ pin output can either be CMOS driven or Open Drain (integrated pull-up) configuration, as
determined by the IRQ_OD register bit. When the I¯R¯Q¯ pin is Open Drain, it is actively driven low when
asserted; the pull-up causes a logic high output when not asserted. The Open Drain configuration
enables multiple devices to share a common Interrupt line with the host processor.
The I¯R¯Q¯ pin output can be masked by setting the IM_IRQ register bit. When the I¯R¯Q¯ pin is masked, it
is held in the logic 1 (or Open Drain) state regardless of any internal interrupt event.
Note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether
the bit is enabled or masked as an input to the corresponding primary interrupt. The primary interrupt
bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of
whether the primary interrupt bit is enabled or masked as an input to the I¯R¯Q¯ pin output.
Note also that if any internal condition is configured to trigger an event other than an Interrupt (eg. the
Watchdog timer triggers Reset), these events are always actioned, regardless of the state of any
interrupt mask bits.
The I¯R¯Q¯ pin output is configured using the register bits described in Table 63.
ADDRESS
R16407
(4017h)
IRQ Config
BIT
LABEL
1
IRQ_OD
0
IM_IRQ
Table 63 IRQ Pin Configuration
DESCRIPTION
IRQ pin configuration
0 = CMOS
1 = Open Drain (integrated pull-up)
IRQ pin output mask
0 = Normal
1 = IRQ output is masked
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PD, February 2012, Rev 4.0
120