WM8960_06 Datasheet, PDF (12/88 Pages) Wolfson Microelectronics plc – Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications

WM8960
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Preliminary Technical Data
MCLK
t MCLKY
Figure 2 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA = +25^oC
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
SYMBOL
TMCLKY
TMCLKDS
CONDITIONS
MIN
33.33
60:40
TYP
MAX
40:60
UNIT
ns
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
w
PTD, September 2006, Rev 2.0
12