WM8991 Datasheet, PDF (108/174 Pages) Wolfson Microelectronics plc – Mobile Multimedia CODEC with Dual-Mode Class AB/D Speaker Driver

WM8991
Pre-Production
Internal clock divide and phase control mechanisms ensure that the BCLK, ADCLRC and DACLRC
edges will occur in a predictable and repeatable position relative to each other and to the data for a
given combination of DAC sample rate, ADC sample rate and BCLK_DIV settings.
See “Clocking and Sample Rates” section for more information.
AUDIO DATA FORMATS (NORMAL MODE)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 66 Right Justified Audio Interface (assuming n-bit word length)
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 67 Left Justified Audio Interface (assuming n-bit word length)
In I²S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
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PP, May 2008, Rev 3.1
108