74HC373 Datasheet, PDF (5/6 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

WS74HC373
Test
From Output ^Point
R_L
Under Test
C_L
(see Note A)
VDD
S1
S2
Parameter
t_PZH
t_en
t_PZL
t_dis
t_PHZ
t_PLZ
tpd or tt
R_L
1kΩ
C_L
50 pF
or
150 pF
1kΩ 50 pF
50 pF
-
or
150 pF
S1
Open
Closed
Open
Closed
S2
Closed
Open
Closed
Open
Open Open
Notes:
A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when
disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when
disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by
generators having the following characteristics:
PRR≤ 1 MHz, Zo = 50Ω, tr=6ns, tf =6ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t_PLZ and t_PHZ are the same as tdis.
F. t_PZL and t_PZH are the same as ten.
G. t_PLH and t_PHL are the same as tpd.
PIN DESCRIPTION
PIN NO.
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
10
1
11
20
1D - 8D
1Q - 8Q
GND
OE
LE
VCC
SYMBOL
DESCRIPTION
Data Inputs
Outputs
Ground (0V)
Output-enable
latch-enable
Positive power supply
OE 1
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND 10
20 VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
11 _LE
Pin Configuration (DIP-20)
3 _1D
4 _2D
7 _3D
8 _4D
13 _5D
14 _6D
17 _7D
18 _8D
11
LE
OE
1
1Q ²
2Q ⁵
3Q ⁶
4Q ⁹
5Q ¹²
6Q ¹⁵
7Q ¹⁶
8Q ¹⁹
Logic Symbol
5