74HC373 Datasheet, PDF (1/6 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

74HC373
Octal Transparent D-type Latches W ith 3-State Outputs
GENERAL DESCRIPTION
74HC373 is fabricated with high-speed silicon
gate CMOS technology. It has the high noise
immunity and low power consumption of standard
CMOS integrated circuits.
The eight latches in 74HC373 devices are
transparent D-type latches. While the latch-enable
(LE) input is high, the Q outputs follow the data (D)
inputs. When LE is low, the Q outputs are latched
at the levels that were set up at the D inputs.
An output-enable input (OE) makes the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-
impedance state and increased drive provide the
capability to drive bus lines without interface or
pull-up components.
OE does not affect the internal operations of
the latches. Old data can be retained or new data
can be entered while the outputs are off.
These 8-bit latches with 3-state outputs are
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bi-directional bus drivers, and
working registers.
FEATURES
• Wide operating supply voltage range: 2-6V
• 8 high-current latches with 3-state outputs in a single package
• Full parallel access for loading
• Low input current: 1µA (Max.)
• Low power consumption: 80µA (Max.)
LOGIC DIAGRAM
1Q (2)
OE (1)
2Q (5)
3Q (6)
4Q (9)
5Q (12)
6Q (15)
7Q (16)
8Q (19)
LE (11)
C1 1D
C1 2D
C1 3D
C1 4D
C1 5D
C1 6D
C1 7D
C1 8D
1D (3)
2D (4)
3D (7)
4D (8)
5D (13)
6D (14)
7D (17)
8D (18)
FUNCTIONAL DESCRIPTION
Truth Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
H = High Level (steady state). L= Low Level (steady state)
X = Irrelevant (any input, including transitions)
Outputs
Q
H
L
Q0
Z
1