W86L387D Datasheet, PDF (9/25 Pages) Winbond – Winbond Host Interface Memory StickTM Bridge

W86L387D
PRELIMINARY
6. REGISTERS
6.1 Register Map
The register in the W86L387D is consisted of command, status, control, received/transmit data buffer,
interrupt, DMA and parallel port registers and READY register in Host interface type 2, these registers
are listed as follows:
Addr
A[3:1]
000
Register Name
(note 1)
Command Reg. (R/W)
Content (note 2)
B1 B1 B1 B1 B1 B1 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
543210
PID code
Data size
0000 - - 0000000000
001
Status Reg. (RO)
Status
--------
00 - - 1010
001
Control Reg. (R/W)
--------
Control
00000101
010
Receive Data Buffer (R/O)
Receive data buffer
0000000000000000
010 Transmit Data Buffer (WO)
Transmit data buffer
XXXXXXXXXXXXXXXX
011
Interrupt Status Reg. (RO)
Interrupt status
--------
1000 - - 00
011
Interrupt Control Reg.
--------
Interrupt control
(R/W)
000 - - - - -
100
Parallel Port Data Reg.
PI[3:0]
PO[3:0]
--------
([15:12]RO, [11:8]R/W)
XXXXXXXX
100
Parallel Port Control Reg. - - - - - - - -
PIEN[3:0]
POEN[3:0]
(R/W)
00000000
101
Ready Control Reg. (R/W) F - - - - - - - - - - - - - - -
0
111
Data Size Reg. (R/W)
- - - - - - - - - - - - - - - 8-
bit
00000000
Note 1:
R/W means the register can be read and write.
RO means the register is read only.
WO means the register is write only.
Note 2:
The data bit in the content is the initial value during hardware reset.
0: the bit value is 0.
1: the bit value is 1.
X: the bit value is unknown.
-: Undefined bit in the register and the value will read 0.
Publication Release Date: July 2001
-6-
Revision 0.50