W9425G6KH-5-TR Datasheet, PDF (7/52 Pages) Winbond – 4 M 4 BANKS 16 BITS DDR SDRAM

W9425G6KH
6. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
28  32,
35  42
A0  A12
Address
Multiplexed pins for row and column address.
Row address: A0  A12.Column address: A0  A8.
Provide the row address for Bank Activate commands, and
the column address and Auto-precharge bit (A10) for
Read/Write commands, to select one location out of the
memory array in the respective bank. A10 is sampled during
a precharge command to determine whether the precharge
applies to one bank (A10 Low) or all banks (A10 High). If
only one bank is to be precharged, the bank is selected by
BA0, BA1. The address inputs also provide the op-code
during a Mode Register Set command. BA0 and BA1 define
which mode register is loaded during the Mode Register Set
command (MRS or EMRS).
26, 27
BA0, BA1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 54, 56,
57, 59, 60, 62,
DQ0  DQ15 Data Input/ Output
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
63, 65
16,51
LDQS,
UDQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
24
CS
Chip Select decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
RAS , CAS , _{Command Inputs Command inputs (along with CS ) define the command}
WE
being entered.
20, 47
LDM, UDM
Write Mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45, 46
CLK,
CLK
All address and control input signals are sampled on the
Differential Clock _{crossing of the positive edge of CLK and negative edge of}
Inputs
CLK .
CKE controls the clock activation and deactivation. When
44
CKE
Clock Enable CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
49
VREF Reference Voltage VREF is reference voltage for inputs.
1, 18, 33
VDD
Power
Power for logic circuit inside DDR SDRAM.
34, 48, 66
VSS
Ground
Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
VDDQ
Power for I/O Separated power from VDD, used for output buffer, to
Buffer
improve noise.
6, 12, 52, 58, 64 VSSQ
Ground for I/O Separated ground from VSS, used for output buffer, to
Buffer
improve noise.
14, 17, 19, 25,
43, 50, 53
NC
No Connection No connection
Publication Release Date: Nov. 17, 2014
Revision: A02
-7-