W681310 Datasheet, PDF (7/36 Pages) Winbond – 3V SINGLE-CHANNEL VOICEBAND CODEC

W681310
6. PIN DESCRIPTION
Pin
Name
Pin Functionality
No.
V_REF
1
This pin is used to bypass the on-chip V_DD/2 voltage reference. It needs to be decoupled to V_SS
through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin.
RO-
2
Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 0.886
volt peak referenced to the analog ground level.
PAI
3
PAO- 4
PAO+ 5
V_DD
6
FSR
7
This pin is the inverting input to the power amplifier. Its DC level is at the V_AG voltage.
Inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially to
1.772 volt peak referenced to the V_AG voltage level.
Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially
to 1.772 volt peak referenced to the V_AG voltage level.
Power supply. This pin should be decoupled to V_SS with a 0.1μF ceramic capacitor.
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR 8 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR 9
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to V_SS. The IDL mode is selected when this pin is tied to V_DD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10 Power up input signal. When this pin is tied to V_DD, the part is powered up. When tied to V_SS,
the part is powered down.
MCLK
11 System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz. For a better performance, it is recommended
to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in
the case of 256 and 512 kHz frequency.
BCLKT 12 PCM transmit bit clock input pin. This pin accepts clocks of 512 kHz to 6176 kHz in the GCI
mode and 256 kHz to 4800kHz in all other PCM modes.
PCMT 13 PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST
14 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
V_SS
15
μ/A-Law 16
AO
17
This is the supply ground. This pin should be connected to 0V.
Compander mode select pin. μ-Law companding is selected when this pin is tied to V_DD. A-Law
companding is selected when this pin is tied to V_SS.
Analog output of the first gain stage in the transmit path.
AI-
18 Inverting input of the first gain stage in the transmit path.
AI+
19 Non-inverting input of the first gain stage in the transmit path.
V_AG
20 Mid-Supply analog ground pin, which supplies a V_DD/2 volt reference voltage for all-analog
signal processing. This pin should be decoupled to V_SS with a 0.01μF capacitor. This pin
becomes high impedance when the chip is powered down.
Publication Release Date: September 2005
-7-
Revision B13