W26020A Datasheet, PDF (7/10 Pages) Winbond – 128K X 16 High Speed CMOS Static RAM

W26020A
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
Address
OE
UB/LB
WE
D OUT
D IN
Write Cycle 2
(OE = VIL Fixed)
CS
UB/LB
WE
D
T WC
WR
T_CW
T_BW
T_AW
WP
T_AS
DW
TDH
T
TCW
WR
TBW
T
T
T
(2)
T
T
T
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Publication Release Date: July 1998
-7-
Revision A3