W9816G6JB Datasheet, PDF (5/42 Pages) Winbond – 512K X 2 BANKS X 16 BITS SDRAM

W9816G6JB
5. BALL DESCRIPTION
Ball-Location Ball Name Function
Description
N6, P7, P6, R6,
R2, P2, P1, N2, A0A10
N1, M2, N7
Address
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
Select bank to activate during row address latch
M1
BA
Bank Address time, or bank to read/write during column address
latch time.
A6, B7, C7, D7,
D6, E7, F7, G7,
G1, F1, E1, D2,
DQ0DQ15
D1, C1, B1, A2,
Data Input/
Output
Multiplexed pins for data input and output.
Disable or enable the command decoder. When
L7
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
K6
Row Address
RAS
Strobe
the clock, RAS , CAS and WE define the
operation to be executed.
K7
Column Address
CAS
Strobe
Referred to RAS
J7
J2/J6
WE
UDQM/
LDQM
Write Enable
Input/Output
Mask
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
K2
CLK
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
L1
CKE
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
A7, R7
VDD
Power
Power for input buffers and logic circuit inside
DRAM.
A1, R1
VSS
Ground
Ground for input buffers and logic circuit inside
DRAM.
B6, C2, E6, F2 VDDQ
Power for I/O Separated power from VDD, used for output buffers
buffer
to improve noise immunity.
B2, C6, E2, F6 VSSQ
Ground for I/O Separated ground from VSS, used for output buffers
buffer
to improve noise immunity.
G2, G6, H1, H2,
H6, H7, J1, K1, NC
L2, L6, M6, M7
No Connection
No connection. (NC pin should be connected to GND
or floating)
Publication Release Date: Jul. 03, 2014
-5-
Revision: A01