W9751G6KB Datasheet, PDF (5/87 Pages) Winbond – 8M  4 BANKS  16 BIT DDR2 SDRAM

W9751G6KB
3. KEY PARAMETERS
SYM.
SPEED GRADE
Bin(CL-tRCD-tRP)
Part Number Extension
@CL = 7
@CL = 6
tCK(avg) Average clock period
@CL = 5
@CL = 4
@CL = 3
tRCD
tRP
tRC
tRAS
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating one bank active-precharge current
Operating one bank active-read-precharge current
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (TCASE ≤ 85°C)
Operating bank interleave read current
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
DDR2-1066 DDR2-800
7-7-7
5-5-5/6-6-6
-18
-25/25I
1.875 nS

7.5 nS

2.5 nS
2.5 nS
7.5 nS
8 nS
3 nS
2.5 nS
7.5 nS
8 nS
3.75 nS
3.75 nS
7.5 nS
8 nS

5 nS

8 nS
13.125 nS
12.5 nS
13.125 nS
12.5 nS
58.125 nS
57.5 nS
45 nS
45 nS
105 mA
90 mA
115mA
100 mA
165 mA
140 mA
200 mA
165 mA
105 mA
95 mA
6 mA
6 mA
245 mA
200 mA
DDR2-667
5-5-5
-3




3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
15 nS
60 nS
45 nS
80 mA
90 mA
125 mA
150 mA
90 mA
6 mA
180 mA
Publication Release Date: Dec. 09, 2011
-5-
Revision A01