W83194R-630_07 Datasheet, PDF (5/15 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194R-630/-630A
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL
PIN
CPUCLK_F
46
CPUCLK [ 0:1 ]
45,43
SDRAM_F
40
SDRAM0/CPU_STOP
#
17
SDRAM1/PCI_STOP#
18
SDRAM2/PD#
SDRAM[3:12]
PCICLK_F/ *FS1
20
21,28,29,31,3
2,34,35,37,38,
41
7
PCICLK 1/ *FS2
8
PCICLK 2/ *MODE
9
PCICLK [ 3:6 ]
11,12,13,14
I/O
OUT
OUT
OUT
I/O
I/O
I/O
OUT
I/O
I/O
I/O
OUT
FUNCTION
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VddLCPU is the supply voltage for these outputs.
This pin will not be stopped by CPU_STOP#
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VddLCPU is the supply voltage for these outputs.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
This pin will not be stopped by CPU_STOP#
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
CPU_STOP# input pin when MODE=0.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
PCI_STOP# input pin when MODE=0.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
PD# input pin when MODE=0.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI free-running clock during normal operation.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI clock during normal operation.
Latched input for MODE at initial power up for input
selection of CPU_STOP#, PCI_STOP# and PD#.
When MODE=1, the above pins are SDRAM clock
outputs. When MODE=0, the pins are inputs ACPI
pins.
PCI clock during normal operation.
Low skew (< 250ps) PCI clock outputs.
Publication Release Date:May 13, 2005
-5-
Revision A1