W78C801 Datasheet, PDF (5/18 Pages) Winbond – 8-BIT MICROCONTROLLER

W78C801
3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit
in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current
for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3
are the same as those of the standard 80C31. The POR register is shown below.
Port Options Register
Bit:
7
6
5
4
3
2
1
0
EP6 EP5
-
HD7 HD6 HD5 HD4 PUP
Mnemonic: POR
Address: 86H
PUP : Enable Port 0 weak pull-up.
HD4-7: Enable pins P3.4 to P3.7 individually with High Drive outputs.
EP5 : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5.
EP6 : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6
Port 4
The W78C801 has one additional bit-addressable I/O port P4 in which the port address is D8H. The
Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and
P4.6 are the alternate function corresponding to pins ALE, PSEN . When program is running in the
internal memory without any access to external memory, ALE and PSEN may be individually
configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable
I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the ALE
and PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be
enabled by software. Care must be taken with the ALE pins when configured as the alternate
functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register
is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O
port P4.5.
Port 4
Bit:
7
6
-
P4.6
Mnemonic: P4
5
P4.5
4
3
2
-
P4.3 P4.2
Address: D8H
1
P4.1
0
P4.0
Interrupt System
The W78C801 has twelve interrupt sources: INT0 and INT1; Timer 0,1; INT2 to INT9. Each interrupt
vectors to a specific location in program memory for its interrupt service routine. Each of these
sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special
Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority
Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used
to awake the device from power down mode. The Port 1 interrupts can be initialized to either active
HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port
1 interrupts. Each flag in IRQ register will be set when an interrupt request is recognized but must be
cleared by software. Note that the interrupt flags have to be cleared before the interrupt service
routine is completed, or else another interrupt will be generated.
Publication Release Date: February 1999
-5-
Revision A3