W83977EG Datasheet, PDF (47/142 Pages) Winbond – WINBOND ISA I/O

W83977EF-AW/W83977EG-AW
TABLE 6-1 UART Register Bit Map
BIT NUMBER
REGISTER ADDRESS
BASE
0
1
2
3
4
5
6
7
+0
BDLAB =
0
+0
BDLAB =
0
Receiver
Buffer
Register
(Read Only)
Transmitter
Buffer
Register
(Write Only)
RBR
TBR
+1
Interrupt
BDLAB = ^{Control ICR}
0
Register
Interrupt
+2
Status
Register
ISR
(Read Only)
UART FIFO
+2
Control
Register
UFR
(Write Only)
UART
+3
Control UCR
Register
Handshake
+4
Control HCR
Register
+5
UART Status
Register
USR
Handshake
+6
Status HSR
Register
+7
User Defined
Register
UDR
+0
Baudrate
BDLAB = ^{Divisor Latch BLL}
1
Low
+1
Baudrate
BDLAB = ^{Divisor Latch BHL}
1
High
RX Data RX Data RX Data
Bit 0
Bit 1
Bit 2
TX Data TX Data TX Data
Bit 0
Bit 1
Bit 2
RBR Data TBR
Ready Empty
Interrupt Interrupt
Enable Enable
(ERDRI) (ETBREI)
USR
Interrupt
Enable
(EUSRI)
"0" if
Interrupt
Pending
Interrupt
Status
Bit (0)
Interrupt
Status
Bit (1)
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
Data
Length
Select
Bit 0
(DLS0)
Data
Terminal
Ready
(DTR)
Data
Length
Select
Bit 1
(DLS1)
Request
to
Send
(RTS)
Multiple
Stop Bits
Enable
(MSBE)
Loopback
RI
Input
RBR Data Overrun
Ready
Error
(RDR) (OER)
Parity Bit
Error
(PBER)
CTS
Toggling
(TCTS)
DSR RI Falling
Toggling Edge
(TDSR) (FERI)
Bit 0
Bit 1
Bit 2
Bit 0
Bit 1
Bit 2
Bit 8
Bit 9
Bit 10
RX Data
Bit 3
TX Data
Bit 3
HSR
Interrupt
Enable
(EHSRI)
Interrupt
Status
Bit (2)**
DMA
Mode
Select
Parity
Bit
Enable
(PBE)
IRQ
Enable
No Stop
Bit
Error
(NSER)
DCD
Toggling
(TDCD)
Bit 3
Bit 3
Bit 11
RX Data RX Data
Bit 4
Bit 5
TX Data TX Data
Bit 4
Bit 5
0
0
0
0
Reserved Reversed
Even
Parity
Enable
(EPE)
Parity
Bit Fixed
Enable
PBFE)
Internal
Loopback
0
Enable
Silent
Byte
Detected
(SBD)
TBR
Empty
(TBRE)
Clear
to Send
(CTS)
Data Set
Ready
(DSR)
Bit 4
Bit 5
Bit 4
Bit 5
Bit 12
Bit 13
RX Data RX Data
Bit 6
Bit 7
TX Data TX Data
Bit 6
Bit 7
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
RX
Interrupt
Active
Level
(LSB)
RX
Interrupt
Active
Level
(MSB)
Set
Silence
Enable
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
0
0
TSR
Empty
(TSRE)
Ring
Indicator
(RI)
RX FIFO
Error
Indication
(RFEI) **
Data
Carrier
Detect
(DCD)
Bit 6
Bit 7
Bit 6
Bit 7
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Publication Release Date: Apr. 2006
-45-
Revision 1.2