W83977EG Datasheet, PDF (3/142 Pages) Winbond – WINBOND ISA I/O

W83977EF-AW/W83977EG-AW
Tables of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 5
2. FEATURES ................................................................................................................................. 6
3. PIN CONFIGURATION ............................................................................................................... 8
4. PIN DESCRIPTION.................................................................................................................... 9
4.1 Host Interface ................................................................................................................. 9
4.2 General Purpose I/O Port ............................................................................................. 11
4.3 Serial Port Interface ...................................................................................................... 11
4.4 Infrared Interface .......................................................................................................... 12
4.5 Multi-Mode Parallel Port ............................................................................................... 13
4.6 FDC Interface ............................................................................................................... 17
4.7 KBC Interface................................................................................................................ 18
4.8 POWER PINS ............................................................................................................... 18
4.9 ACPI Interface............................................................................................................... 18
5. FDC FUNCTIONAL DESCRIPTION ......................................................................................... 19
5.1 W83977EF/EG FDC ..................................................................................................... 19
5.1.1 AT interface ..................................................................................................................19
5.1.2 FIFO (Data) ..................................................................................................................19
5.1.3 Data Separator .............................................................................................................20
5.1.4 Write Precompensation ................................................................................................20
5.1.5 Perpendicular Recording Mode ....................................................................................20
5.1.6 FDC Core .....................................................................................................................21
5.1.7 FDC Commands...........................................................................................................21
5.2 Register Descriptions.................................................................................................... 32
5.2.1 Status Register A (SA Register) (Read base address + 0)...........................................32
5.2.2 Status Register B (SB Register) (Read base address + 1)...........................................34
5.2.3 Digital Output Register (DO Register) (Write base address + 2) ..................................36
5.2.4 Tape Drive Register (TD Register) (Read base address + 3).......................................36
5.2.5 Main Status Register (MS Register) (Read base address + 4).....................................37
5.2.6 Data Rate Register (DR Register) (Write base address + 4) ........................................37
5.2.7 FIFO Register (R/W base address + 5) ........................................................................39
5.2.8 Digital Input Register (DI Register) (Read base address + 7).......................................41
5.2.9 Configuration Control Register (CC Register) (Write base address + 7) ......................42
6. UART PORT ............................................................................................................................. 44
6.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) ............................ 44
6.2 Register Address .......................................................................................................... 44
6.2.1 UART Control Register (UCR) (Read/Write) ................................................................44
6.2.2 UART Status Register (USR) (Read/Write) ..................................................................47
6.2.3 Handshake Control Register (HCR) (Read/Write) ........................................................48
6.2.4 Handshake Status Register (HSR) (Read/Write)..........................................................48
6.2.5 UART FIFO Control Register (UFR) (Write only)..........................................................49
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