W971GG6JB_13 Datasheet, PDF (45/87 Pages) Winbond – 8M X 8 BANKS X 16 BIT DDR2 SDRAM

W971GG6JB
10.11.2 AC Characteristics and Operating Condition for -25/25L/25I/25A/25K/-3/-3A speed grades
Notes: 1-3 and 45-47 apply to the entire table
SYM.
tRCD
tRP
tRC
tRAS
tRFC
tREFI
SPEED GRADE
Bin(CL-tRCD-tRP)
PARAMETER
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Auto Refresh to Active/Auto Refresh command
period
-40°C ≤ TCASE ≤ 85°C*
Average periodic
refresh Interval
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
95°C < TCASE ≤ 105°C*
DDR2-800
(-25/25L/25I/25A/25K)
5-5-5
MIN.
MAX.
12.5

12.5

52.5

40
70000
127.5


7.8

7.8

3.9

3.9
DDR2-667
(-3/-3A)
5-5-5
MIN. MAX.
15

15

55

40
70000
UNITS²⁵ NOTES
nS
23
nS
23
nS
23
nS
4,23
127.5

nS
5

7.8
μS
5

7.8
μS
5

3.9
μS
5,6


μS
5,6
tCCD
tCK(avg)
tCH(avg)
tCL(avg)
CAS to CAS command delay
tCK(avg) @ CL=3
Average clock period
tCK(avg) @ CL=4
tCK(avg) @ CL=5
tCK(avg) @ CL=6
Average clock high pulse width
Average clock low pulse width
2

2

nCK
5
8
5
8
nS
30,31
3.75
8
3.75
8
nS
30,31
2.5
8
3
8
nS
30,31
2.5
8


nS
30,31
0.45
0.55
0.45
0.55 tCK(avg) 30,31
0.45
0.55
0.45
0.55 tCK(avg) 30,31
tAC _{DQ output access time from CLK/ CLK}
-400
400
-450
450
pS
35
tDQSCK
tDQSQ
tCKE
tRRD
tFAW
tWR
tDAL
tWTR
tRTP
DQS output access time from CLK / CLK
DQS-DQ skew for DQS & associated DQ signals
CKE minimum high and low pulse width
Active to active command period for 2KB page size
Four Activate Window for 2KB page size
Write recovery time
Auto-precharge write recovery + precharge time
Internal Write to Read command delay
Internal Read to Precharge command delay
-350

3
10
45
15
WR + tnRP
7.5
7.5
tIS (base) Address and control input setup time
175
tIH (base) Address and control input hold time
250
tIS (ref) Address and control input setup time
375
tIH (ref) Address and control input hold time
tIPW
tDQSS
tDSS
tDSH
tDQSH
tDQSL
Address and control input pulse width for each input
DQS latching rising transitions to associated clock
edges
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
DQS input high pulse width
DQS input low pulse width
375
0.6
-0.25
0.2
0.2
0.35
0.35
350
-400
400
200

240

3


10


50


15

 WR + tnRP 

7.5


7.5


200


275


400


400


0.6

0.25
-0.25
0.25

0.2


0.2


0.35


0.35

pS
35
pS
13
nCK
7
nS
8,23
nS
23
nS
23
nCK
24
nS
9,23
nS
4,23
pS
10,26,
40,42,43
pS
11,26,
40,42,43
pS
10,26,
40,42,43
pS
11,26,
40,42,43
tCK(avg)
tCK(avg)
28
tCK(avg)
28
tCK(avg)
28
tCK(avg)
tCK(avg)
* -40°C ≤ TCASE ≤ 85°C is for 25I/25A/25K/-3A grade only, 95°C < TCASE ≤ 105°C is for 25K grade only.
- 45 -
Publication Release Date: Sep. 24, 2013
Revision A09