W29GL128C Datasheet, PDF (4/64 Pages) Winbond – 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL128C
8.1 Absolute Maximum Stress Ratings............................................................................... 29
8.2 Operating Temperature and Voltage ............................................................................ 29
8.3 DC Characteristics ........................................................................................................ 30
8.4 Switching Test Circuits.................................................................................................. 31
8.4.1 Switching Test Waveform ............................................................................................... 31
8.5 AC Characteristics ........................................................................................................ 32
8.5.1 Instruction Write Operation ............................................................................................. 33
8.5.2 Read / Reset Operation .................................................................................................. 34
8.5.3 Erase/Program Operation ............................................................................................... 36
8.5.4 Write Operation Status....................................................................................................45
8.5.5 WORD/BYTE CONFIGURATION (#BYTE)..................................................................... 49
8.5.6 DEEP POWER DOWN MODE........................................................................................51
8.5.7 WRITE BUFFER PROGRAM..........................................................................................51
8.6 Recommended Operating Conditions........................................................................... 52
8.6.1 At Device Power-up ........................................................................................................ 52
8.7 Erase and Programming Performance ......................................................................... 53
8.8 Data Retention .............................................................................................................. 53
8.9 Latch-up Characteristics ............................................................................................... 53
8.10 Pin Capacitance............................................................................................................ 53
9
PACKAGE DIMENSIONS ......................................................................................................... 54
9.1 TSOP 56-pin 14x20mm ................................................................................................ 54
9.2 Low-Profile Fine-Pitch Ball Grid Array, 64-ball 11x13mm (LFBA64) ............................ 55
10 ORDERING INFORMATION..................................................................................................... 56
10.1 Ordering Part Number Definitions................................................................................. 56
10.2 Valid Part Numbers and Top Side Marking .................................................................. 57
11 HISTORY .................................................................................................................................. 58
Figure 3-1
Figure 3-2
Figure 4-1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
List of Figures
LFBGA64 TOP VIEW (FACE DOWN) ............................................................................ 2
56-PIN STANDARD TSOP (TOP VIEW) ........................................................................ 2
Block Diagram................................................................................................................. 3
Enhanced Sector Protect/Un-protect IPB Program Algorithm ...................................... 15
Lock Register Program Algorithm................................................................................. 16
IPB Program Algorithm ................................................................................................. 18
Maximum Negative Overshoot ..................................................................................... 29
Maximum Positive Overshoot ....................................................................................... 29
Switch Test Circuit ........................................................................................................ 31
Switching Test Waveform ............................................................................................. 31
Instruction Write Operation Waveform.......................................................................... 33
Read Timing Waveform ................................................................................................ 34
#RESET Timing Waveform........................................................................................... 35
Automatic Chip Erase Timing Waveform...................................................................... 36
Automatic Chip Erase Algorithm Flowchart .................................................................. 37
Automatic Sector Erase Timing Waveform................................................................... 38
Automatic Sector Erase Algorithm Flowchart ............................................................... 39
Erase Suspend/Resume Flowchart .............................................................................. 40
Automatic Program Timing Waveform.......................................................................... 41
Accelerated Program Timing Waveform....................................................................... 41
CE# Controlled Write Timing Waveform....................................................................... 42
ii