W49L102 Datasheet, PDF (3/21 Pages) Winbond – 64K X 16 CMOS 3.3V FLASH MEMORY

Preliminary W49L102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49L102 is controlled by CE and OE, both of which have to be low for the
host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is
de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000 hex to 1FFF hex.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block can not be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will only affect the main memory.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the
output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Input Levels
While operating with a 3.0V−3.6V power supply, the address inputs and control inputs (OE, CE and
WE ) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to 3.6V.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the main
memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as
before the chip erase operation). The entire memory array (main memory and boot block) will be
erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not
activated. The device will automatically return to normal read mode after the erase operation
completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Main Memory Erase Operation
The main memory erase mode can be initiated by a six-word command sequence. After the
command loading cycle, the device enters the internal main-memory erase mode, which is
automatically timed and will be completed in a fast 100 mS (typical). The host system is not required
Publication Release Date: June 1999
-3-
Revision A1