W49L102 Datasheet, PDF (13/21 Pages) Winbond – 64K X 16 CMOS 3.3V FLASH MEMORY

Preliminary W49L102
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
SYM.
TRC
TCE
TAA
TOE
TCLZ
TOLZ
TCHZ
TOHZ
TOH
W49L102-55
MIN. MAX.
55
-
-
55
-
55
-
30
0
-
0
-
-
25
-
25
0
-
W49L102-70
MIN. MAX.
70
-
-
70
-
70
-
35
0
-
0
-
-
30
-
30
0
-
W49L102-90
MIN. MAX.
90
-
-
90
-
90
-
40
0
-
0
-
-
30
-
30
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle Timing Parameters
PARAMETER
Address Setup Time
Address Hold Time
WE and CE Setup Time
WE and CE Hold Time
OE High Setup Time
OE High Hold Time
CE Pulse Width
WE Pulse Width
WE High Width
Data Setup Time
Data Hold Time
Word Programming Time
Erase Cycle Time
SYMBOL
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
TDH
TBP
TEC
MIN.
10
100
0
0
0
0
200
200
200
100
10
-
-
TYP.
-
-
-
-
-
-
-
-
-
-
-
30
0.1
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
MAX.
-
-
-
-
-
-
-
-
-
-
-
50
1
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
Sec.
- 13 -
Publication Release Date: June 1999
Revision A1