W83L785R Datasheet, PDF (27/38 Pages) Winbond – WINBOND H/W MONITORING IC FOR NOTEBOOK

W83L785R/W83L785G
OVT# Property Select  Index 50h, continued.
BIT
NAME
3 Reserved
2 EN_OVT2
READ/WRITE
Read/Write
Read/Write
1 EN_OVT1
Read/Write
0 OVTPOL
Read/Write
DESCRIPTION
Reserved
Enable temperature sensor 2 over-temperature (OVT)
output if set to 1. Default 0, disable OVT2 output through
pin OVT#. The pin OVT# is wire OR with OVT1. Default
disable temperature 2 OVT# function.
Enable temperature sensor 1 over-temperature (OVT)
output if set to 1. Default 0, disable OVT1 output through
pin OVT#. The pin OVT# is wire OR with OVT2. Default
disable temperature 1 OVT# function.
Over-Temperature Polarity. Write 1, OVT# active high.
Write 0, OVT# active low. Default 0.
7.18 SMI# Property Select  Index 51h
Power on - <7:0> --0000, 0100 b
BIT
NAME
READ/WRITE
DESCRIPTION
7-4 Reserved
Read/Write Reserved.
3-2 TEMP_SMI_MD[1:0] Read/Write Temperature SMI Mode Select.
<00> - Comparator Interrupt Mode:
Temperature 1/2 exceeds T_O (Over-temperature) limit
causes and interrupt and this interrupt will be reset
by reading all the Interrupt Status.
<01> - Two Time Interrupt Mode:(Default)
This bit use in temperature sensor 1/2 interrupt mode
with hysteresis and T_O type. Temperature exceeding
T_O, causes an interrupt and then temperature going
below T_HYST will also cause another interrupt if the
previous interrupt has been reset by reading all the
interrupt Status Register. Once an interrupt event has
occurred by exceeding T_O, then reset, if the
temperature remains above the T_HYST.
<10> - One Time Interrupt Mode:
This bit use in temperature sensor 1/2 interrupt mode
with hysteresis type. Temperature exceeding T_O
(Over-temperature) causes an interrupt and then
temperature going below T_HYST (Hysteresis
temperature) will not cause an interrupt. Once an
interrupt event has occurred by exceeding T_O, then
going below T_HYST, and interrupt will not occur again
until the temperature exceeding T_O.
1 EN_SMI#
Read/Write
Enable SMI# Output. A one enables the SMI#
Interrupt output.
0 SMIPOL
Read/Write
SMI# Polarity. Write 1, SMI# active high. Write 0,
SMI# active low. Default 0.
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Publication Release Date: Apr. 2006
Revision 1.1