W39V040FC Datasheet, PDF (27/36 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V040FC
16. FWH INTERFACE MODE AC CHARACTERISTICS
16.1 AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
CONDITIONS
0.6 VDD to 0.2 VDD
1 V/nS
0.4VDD / 0.4VDD
1 TTL Gate and CL = 10 pF
16.2 Read/Write Cycle Timing Parameters
(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W39V040FC
MIN.
MAX.
Clock Cycle Time
Input Set Up Time
Input Hold Time
Clock to Data Valid
TCYC
30
-
TSU
7
-
THD
0
-
TKQ
2
11
Note: Minimum and Maximum time have different load. Please refer to PCI specification.
UNIT
nS
nS
nS
nS
16.3 Reset Timing Parameters
PARAMETER
VDD stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
Reset Active to Output Float
Reset Inactive to Input Active
SYMBOL
TPRST
TKRST
TRSTP
TRSTF
TRST
MIN.
1
100
100
-
10
TYP.
-
-
-
-
-
MAX.
-
-
-
50
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Please refer to the AC testing condition.
UNIT
mS
μS
nS
nS
μS
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Publication Release Date: Apr. 11, 2006
Revision A1