W27E520 Datasheet, PDF (2/16 Pages) Winbond – 64K X 8 ELECTRICALLY ERASABLE EPROM

W27E520
FUNCTIONAL DESCRIPTION
Read Mode
Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27E520
has one OE/VPP and one ALE (address_latch_enable) control functions. The ALE makes lower
address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be
used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed.
OE/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the
address access time (TACC) is equal to the delay from ALE to output (TCE), and data are available at
the outputs TOE after the falling edge of OE/VPP, if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E520 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise OE /VPP to VPE (13V), VDD = VDE (6.5V),
A9 = VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed
low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by
programming two consecutive commands into the device and then enter Erase mode. The two
commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. =
2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is
50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the
device can force the device enter Normal Read Mode again.
Program Mode
Programming is the only way to change cell data from "1" to "0." The program mode is entered when
OE/VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and
the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.
Program Verify Mode
The device will enter the Program Verify Mode automatically after Program Mode. Only power down
the device can force the device enter Normal Read Mode again.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the
ALE and OE /VPP pins, the W27E520 may have common inputs.
Standby Mode
The standby mode significantly reduces VDD current. This mode is entered when ALE and OE /VPP
keep high. In standby mode, all outputs are in a high impedance state.
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