W78ERD2_07 Datasheet, PDF (19/76 Pages) Winbond – 8-BIT MICROCONTROLLER

W78ERD2/W78ERD2A
BIT
NAME
FUNCTION
7
6–2
1
0
W: SWRESET
R: REBOOT
-
FBOOTSL
FPROGEN
When FBOOTSL and FPROGEN are set to 1, set this bit to 1 to force the
microcontroller to reset to the initial condition, just like power-on reset.
This action re-boots the microcontroller and starts normal operation.
Read this bit to determine whether or not a hardware reboot is in progress.
Reserved
Program Location Selection. This bit should be set before entering ISP
mode.
0: The Loader Program is in the 64-KB AP Flash EPROM. The 4-KB LD
Flash EPROM is the destination for re-programming.
1: The Loader Program is in the 4-KB memory bank. The 64-KB AP Flash
EPROM is the destination for re-programming.
FLASH EPROM Programming Enable.
1: Enable in-system programming mode. In this mode, erase, program and
read operations are achieved during device enters idle state.
0: Disable in-system programming mode. The on-chip flash memory is
read-only.
CHPCON has an unrestricted read access, however, the write access is protected by timed-access
protection. See the section of timed-access protection for more information.
External Interrupt Control
Bit:
7
6
5
4
3
2
1
0
PX3 EX3
IE3
IT3
PX2 EX2
IE2
IT2
Mnemonic: XICON Address: C0h
BIT
NAME
FUNCTION
7
PX3
1: Set the priority of external interrupt INT3 one level higher.
6
EX3
1: Enable external interrupt INT3 .
5
IE3
Interrupt INT3 flag. This bit is set and cleared automatically by the hardware
when the interrupt is detected and processed.
1: INT3 is falling-edge triggered
4
IT3
0: INT3 is low-level triggered
3
PX2
1: Set the priority of external interrupt INT2 one level higher.
2
EX2
1: Enable external interrupt INT2 .
1
IE2
Interrupt INT2 flag. This bit is set and cleared automatically by the hardware
when the interrupt is detected and processed.
0
IT2
1: INT2 is falling-edge triggered
0: INT2 is low-level triggered
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Publication Release Date: February 14, 2007
Revision A10