W25X10BL Datasheet, PDF (19/53 Pages) Winbond – 1M-BIT, 2M-BIT AND 4M-BIT 2.5V SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI

W25X10BL/20BL/40BL
9.2.7 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register) can be written to. All other
Status Register bit locations are read-only and will not be affected by the Write Status Register
instruction. The Status Register bits are shown in figure 3 and described in 9.1.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously
have been executed for the device to accept the Write Status Register Instruction (Status Register bit
WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the
instruction code “01h”, and then writing the status register data byte as illustrated in figure 8.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
Upon power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register
bit values will be restored when power on again.
To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth bit
of data that is clocked in. If this is not done the Write Status Register instruction will not be executed.
During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the
Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions
again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the
Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Please refer to 9.1 for detailed Status Register Bit descriptions. Factory default for all status Register
bits are 0.
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Publication Release Date: October 14, 2009
Preliminary -- Revision A